C509-L_97 Datasheet, PDF (137/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.3.4.4 Compare Function of Registers CM0 to CM7
The CCU of the C509-L contains another set of eight compare registers and an additional timer, the
compare timer, and some control SFRs. These compare registers and the compare timer are mainly
dedicated to PWM applications.
The compare registers CM0 to CM7, however, are not permanently assigned to the compare timer,
each register may individually be configured to work either with timer 2 or the compare timer. This
flexible assignment of the CMx registers allows an independent use of two time bases whereby
different application requirements can be met. Any CMx register connected to the compare timer
automatically works in compare mode 0 e.g. to provide fast PWM with low CPU intervention. CMx
registers which are assigned to timer 2, operate in compare mode 1. This allows the CPU to control
the compare output transitions directly.
The assignment of the eight registers CM0 to CM7 to either timer 2 or to the compare timer is done
by a multiplexer which is controlled by the bits in the SFR CMSEL. The compare function itself can
individually be enabled in the SFR CMEN. These two registers are not bit-addressable. This means,
that the value of single bits can only be changed by AND-ing or OR-ing the register with a certain
mask.
Special Function Register CMSEL (Address F7H)
Special Function Register CMEN (Address F6H)
Reset Value : 00H
Reset Value : 00H
MSB
LSB
Bit No. 7
6
5
4
3
2
1
0
F7H
.7
.6
.5
.4
.3
.2
.1
.0 CMSEL
7
6
5
4
3
2
1
0
F6H
.7
.6
.5
.4
.3
.2
.1
.0 CMEN
Bit
CMSEL.7 - 0
CMEN.7 - 0
Function
Select bits for CMx registers (x = 0-7)
When set, the CMLx/CMHx registers are assigned to the compare timer
and compare mode 0 is enabled. The compare registers are assigned to
timer 2 if CMSELx = 0. In this case compare mode 1 is selected.
Enable bits for compare registers CMx (x = 0 - 7)
When set, the compare function is enabled and led to the output lines of
port 4.
Semiconductor Group
6-59
1997-10-01