C509-L_97 Datasheet, PDF (193/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
Depending on the application, typically there are three software methods to handle the A/D
conversion in the C509-L.
– Software delay
The machine cycles of the A/D conversion are counted and the program executes a software
delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle. This is
the fastest method to get the result of an A/D conversion.
– Polling BSY bit
The BSY bit is polled and the program waits until BSY=0. Attention : a polling JB instruction
which is two machine cycles long, possibly may not recognize the BSY=0 condition during the
write result cycle in the continuous conversion mode.
– A/D conversion interrupt
After the start of an A/D conversion the A/D converter interrupt is enabled. The result of the
A/D conversion is read in the interrupt service routine. If other SAB-C509 interrupts are
enabled, the interrupt latency must be regarded. Therefore, this software method is the
slowest method to get the result of an A/D conversion.
Depending on the oscillator frequency of the C509-L and the selected divider ratios of the A/D
converter prescalers the total time of an A/D conversion is calculated according to table 6-13. The
minimum conversion time is 6 µs.
Table 6-13
A/D Conversion Times
Conversion Clock Sample Clock
Prescaler
Prescaler
3.5 MHz
ADCL1 ADCL0 ADST1 ADST0 _{fADC tADCC}
[MHz] [µs]
Processor Clock Rate
8 MHz
12 MHz
f_ADC t_ADCC f_ADC t_ADCC
[MHz] [µs] [MHz] [µs]
16 MHz
f_ADC t_ADCC
[MHz] [µs]
0
0
0
0 0.875 13.7 2
6
3
4
4
3
0
1
16
7
4.7
3.5
1
0
20.6
9
6
4.5
1
1
29.7
13
8.7
6.5
0
1
0
0 0.438 27.4 1
12 1.5 8
2
6
0
1
32
14
9.3
7
1
0
41.1
18
12
9
1
1
59.4
26
17.3
13
1
0
0
0 0.219 54.9 0.5 24 0.75 16 1
12
0
1
64
28
18.7
14
1
0
82.3
36
24
18
1
1
118.9
52
34.7
26
1
1
0
0 0.109 109.7 0.25 48 0.375 32 0.5 24
0
1
128
56
37.3
28
1
0
164.6
72
48
36
1
1
237.7
104
69.3
52
Note : The shaded prescaler/frequency combinations must not be used. Reason : f_ADC > 2 MHz.
Semiconductor Group
6-115
1997-10-01