C509-L_97 Datasheet, PDF (54/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

External Bus Interface
C509-L
4.1.2 Timing
The timing of the external bus interface, in particular the relationship between the control signals
ALE, PSEN, RD, WR and information on port 0 and port 2, is illustrated in figure 4-1 a) and b).
Data memory:
in a write cycle, the data byte to be written appears on port 0 just before WR is
activated and remains there until after WR is deactivated. In a read cycle, the
incoming byte is accepted at port 0 before the read strobe is deactivated.
Program memory: Signal PSEN functions as a read strobe.
4.1.3 External Program Memory Access
The external program memory is accessed whenever signal EA is active (low): Due to the 64K
internal ROM, no mixed internal/external program memory execution is possible.
When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an
output function and may not be used for general-purpose I/O. The contents of the port 2 SFR
however is not affected. During external program memory fetches port 2 lines output the high byte
of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR
(depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri).
When the C509-L executes instructions from external program memory, port 2 is at all times
dedicated to output the high-order address byte. This means that port 0 and port 2 of the C509-L
can never be used as general-purpose I/O.
4.1.4 PSEN, Program Store Enable
The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the
CPU is accessing external program memory, PSEN is activated twice every cycle (except during a
MOVX instruction) no matter whether or not the byte fetched is actually needed for the current
instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle,
including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN
cycle, including activation and deactivation of ALE and PSEN takes 3 oscillator periods. The
execution sequence for these two types of read cycles is shown in figure 4-1 a) and b).
4.1.5 Overlapping External Data and Program Memory Spaces
In some applications it is desirable to execute a program from the same physical memory that is
used for storing data. In the C509-L the external program and data memory spaces can be
combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active
low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster
than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.
Semiconductor Group
4-2
1997-10-01