C509-L_97 Datasheet, PDF (235/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C509-L
9.7 Hardware Power Down Mode Reset Timing
The following figures show timing diagrams for entering (figure 8-1) and leaving (figure 8-2) the
hardware power down mode. If there is only a short signal at pin HWPD (i.e. HWPD is sampled
active only once), then a complete internal reset is executed. Afterwards the normal program
execution starts again (figure 8-3).
Note: Delay time caused by internal logic is not included.
The RESET pin overrides the hardware power down function, i.e. if RESET becomes active during
hardware power down it is terminated and the device performs the normal reset function. Thus, pin
RESET has to be inactive during hardware power down mode.
Semiconductor Group
9-10
1997-10-01