C509-L_97 Datasheet, PDF (27/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
3.1 Program Memory, “Code Space”
Besides the internal Boot ROM, the C509-L has no internal program memory (ROM). In normal
mode the program memory of the C509-L is located externally and can be expanded up to 64 Kbyte.
In the normal mode the C509-L fetches all instructions from the external program memory.
Therefore, the pin EA of the C509-L must be always tied to low level.
The Boot ROM includes a bootstrap loader program for the bootstrap mode of the C509-L. The
software routines of the bootstrap loader program allow the easy and quick programming or loading
of the internal XRAM (F400H to FFFFH) via the serial interface while the MCU is in-circuit. This
allows to transfer custom routines to the XRAM, which will program an external 64 KByte FLASH
memory. The routines of the bootstrap loader program may be executed or even can be blocked to
prevent unauthorized persons from reading out or writing to the external FLASH memory.
Therefore, the bootstrap loader checks an external FLASH memory for existing custom software
and executes it. The bootstrap loader program is described in detail in chapter 10.
3.2 Data Memory, “Data Space”
The data memory address space consists of an internal and an external memory space. The
internal data memory is divided into three physically separate and distinct blocks: the lower 128
bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area.
While the upper 128 bytes of data memory and the SFR area share the same address locations,
they are accessed through different addressing modes. The lower 128 bytes of data memory can
be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be
accessed through register indirect addressing; the special function registers are accessible through
direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers,
occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through
2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the
internal data memory address space, and the stack depth can be expanded up to 256 bytes.
The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions
that use a 16-bit or an 8-bit address. The internal XRAM is also located in the external data memory
area and must be accessed by external data memory instructions (MOVX). The XRAM can also
serve as code memory in the XRAM mode and in the FLASH programming mode. In these modes
program code which has been prior loaded via the bootstrap loader program, is executed in the
XRAM.
3.3 General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose
registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program
status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the
PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines
or interrupt service routines.
The 8 general purpose registers of the selected register bank may be accessed by register
addressing. With register addressing the instruction op code indicates which register is to be used.
For indirect addressing R0 and R1 are used as pointer or index register to address internal or
external memory (e.g. MOV @R0).
Semiconductor Group
3-2
1997-10-01