C509-L_97 Datasheet, PDF (32/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Memory Organization
C509-L
3.4.4 Bootstrap Mode Configuration
In the Bootstrap Mode the Boot ROM and the external FLASH/ROM/EPROM are mapped into the
code memory area. 61K byte external SRAM as well as 3K byte internal data memory (XRAM) are
provided in the external data memory area. The external program memory is controlled by the
PSEN/RDF signal. Read and write accesses to the external data memory are controlled by the RD
and WR pins of port 3.
The Bootstrap Mode is entered by keeping the pin PRGEN at a logic high level during the rising
edge of the external RESET or HWPD signal (→ PRGEN1=1). The locations of the code- and data
memory in the external boot-strap mode are shown in figure 3-5.
Figure 3-5
Locations of Code- and Data Memory in Bootstrap Mode
In Bootstrap Mode the internal XRAM is selected automatically as data memory. When leaving the
Bootstrap Mode, the XRAM is disabled (only if the XMAP0 bit was not cleared by software before).
Semiconductor Group
3-7
1997-10-01