C509-L_97 Datasheet, PDF (64/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

External Bus Interface
C509-L
4.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)
The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect
addressing. These instructions are:
– MOVX A, @DPTR (Read)
– MOVX @DPTR, A (Write)
For accessing the XRAM, the effective address stored in DPTR must be in the range of F400H to
FFFFH.
4.4.3 Accesses to XRAM using the Registers R0/R1
The 8051 architecture provides also instructions for accesses to external data memory range which
use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are:
MOVX
MOVX
A, @ Ri
@Ri, A
(Read)
(Write)
In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as page
register which selects pages of 256-Byte. However, the distinction, whether Port 2 is used as
general purpose I/0 or as “page address” is made by the external system design. From the device's
point of view it cannot be decided whether the Port 2 data is used externally as address or as I/0
data.
Hence, a special page register is implemented into the C509-L to provide the possibility of
accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same function
for the XRAM as Port 2 for external data memory.
Special Function Register XPAGE (Address 91H)
Reset Value : 00H
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
91H
.7
.6
.5
.4
.3
.2
.1
.0 ^XPAGE
Bit
XPAGE.7-0
Function
XRAM high address
XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are
used to access the internal XRAM.
Figures 4-4 and 4-6 show the dependencies of XPAGE- and Port 2 - addressing in order to explain
the differences in accessing XRAM/CAN controller, ext. RAM or what is to do when Port 2 is used
as an I/O-port.
Semiconductor Group
4-12
1997-10-01