C509-L_97 Datasheet, PDF (222/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Fail Save Mechanisms
C509-L
8.1.3 Starting the Watchdog Timer
Immediately after start (see next section for the start procedure), the watchdog timer is initialized to
the reload value programmed to WDTREL.0 - WDTREL.6. After an external hardware or HWPD
reset, an oscillator power on reset, or a watchdog timer reset, register WDTREL is cleared to 00H.
WDTREL can be loaded by software at any time.
There are two ways to start the watchdog timer depending on the level applied to pin PE/SWD. This
pin serves two functions, because it is also used for blocking the power saving modes (see also
chapter 9).
8.1.3.1 The First Possibility of Starting the Watchdog Timer
The automatic start of the watchdog timer directly after an external HW reset is a hardware start
initialized by strapping pin PE/SWD to V_CC. In this case the power-saving modes (power-down
mode, idle mode and slow-down mode) are also disabled and cannot be started by software.
The self-start of the watchdog timer by a pin option has been implemented to provide high system
security in electrically very noisy environments.
Note: The automatic start of the watchdog timer is only performed if PE/SWD (power-save enable/
start watchdog timer) is held at high level while reset is active. A positive transition at this pin
during normal program execution will not start the watchdog timer.
Furthermore, when using the hardware start, the watchdog timer starts running with its
default time- out period. The value in the reload register WDTREL, however, can be
overwritten at any time to set any time-out period desired.
8.1.3.2 The Second Possibility of Starting the Watchdog Timer
The watchdog timer can also be started by software. Setting of bit SWDT in special function register
IEN1 starts the watchdog timer. Using the software start, the timeout period can be programmed
before the watchdog timer starts running.
Note that once the watchdog timer has been started it cannot be stopped by anything but an
external hardware reset through pin RESET with a low level applied to pin PE/SWD.
Semiconductor Group
8-4
1997-10-01