C509-L_97 Datasheet, PDF (159/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
In this case the error flag can be used to indicate whether the values in the registers MD0 to MD5
are the expected ones or whether the operation must be repeated. For a multiplication/division, the
error flag mechanism is automatically enabled with the first write instruction to MD0 (phase 1).
According to the above described programming sequences, this is the first action for every type of
calculation. The mechanism is disabled with the final read instruction from MD3 or MD5 (phase 3).
Every instruction which rewrites MD0 (and therefore tries to start a new calculation) in phases 1
through 3 of the same process sets the error flag.
The same applies for any shift operation (normalize, shift left/right). The error flag is set if the user’s
program reads one of the relevant registers (MD0 to MD3) or if it writes to MD0 again before the
shift operation has been completed.
Please note that the error flag mechanism is just an option to monitor the MDU operation. lf the
user’s program is designed such that an MDU operation cannot be interrupted by other calculations,
then there is no need to pay attention to the error flag. In this case it is also possible to change the
order in which the MDx registers are read, or even to skip some register read instructions.
Concerning the shift or normalize instructions, it is possible to read the result before the complete
execution time of six machine cycles has passed (e.g. when a small number of shifts has been
programmed). All of the above “illegal” actions would set the error flag, but on the other hand do not
affect a correct MDU operation. The user has just to make sure that everything goes right.
The error flag (MDEF) is located in ARCON and can be read only. It is automatically cleared after
being read.
Semiconductor Group
6-81
1997-10-01