C509-L_97 Datasheet, PDF (157/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
There is no restriction on the time within which a calculation must be completed. The CPU is allowed
to continue the program simultaneously to phase 2 and to fetch the result bytes at any time.
lf the user’s program takes care that interrupting a calculation is not possible, monitoring of the
calculation process is probably not needed. In this case, only the write sequence must be observed.
Any new write access to MD0 starts a new calculation, no matter whether the read-out of the former
result has been completed or not.
6.4.4 Normalize and Shift
Register ARCON controls an up to 32-bit wide normalize and shift operation in registers MD0 to
MD3. It also contains the overflow flag and the error flag which are described in the next two
sections.
Write Sequence
– A write-to-MD0 is also the first transfer to be done for normalize and shift. This write resets
the MDU and triggers the error flag mechanism (see below).
– To start a shift or normalize operation the last write must access register ARCON.
Read Sequence
– The order in which the first three registers MD0 to MD2 are read is not critical
– The last read from MD3 determines the end of a whole shift or normalize procedure and
releases the error flag mechanism.
Note: Any write access to ARCON triggers a shift or normalize operation and therefore changes the
contents of registers MD0 to MD3!
Normalizing
Normalizing is done on an integer variable stored in MD0 (least significant byte) to MD3 (most
significant byte). This feature is mainly meant to support applications where floating point arithmetic
is used. “To normalize” means, that all reading zeroes of an integer variable in registers MD0 to
MD3 are removed by shift left operations. The whole operation is completed when the MSB (most
significant bit) contains a ‘1’.
To select a normalize operation, the five bit field ARCON.0 to ARCON.4 must be cleared. That
means, a write-to-ARCON instruction with the value XXX0 0000B starts the operation.
After normalizing, bits ARCON.0 to ARCON.4 contain the number of shift left operations which were
done. This number may further on be used as an exponent. The maximum number of shifts in a
normalize operation is 31 (= 2⁵ – 1). The operation takes six machine cycles at most, that means 3
microseconds at 12 MHz.
Shifting
In the same way - by a write-to-ARCON instruction - a shift left/right operation can be started. In this
case register bit SLR (ARCON.5) has to contain the shift direction, and ARCON.0 to ARCON.4 the
shift count (which must not be 0, otherwise a normalize operation would be executed). During shift,
zeroes come into the left or right end of the registers MD0 or MD3, respectively.
Semiconductor Group
6-79
1997-10-01