C509-L_97 Datasheet, PDF (71/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Reset / System Clock
C509-L
The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which,
under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is
typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is
generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started
up properly and that at least two machine cycles have passed before the reset signal goes inactive.
Figure 5-1
Reset Circuitries
A correct reset leaves the processor in a defined state. The program execution starts at location
0000H. Depending on the state of the PRGEN pin, either external ROM/EPROM is accessed
(Normal Mode) or the C509-L starts with the bootstrap loader program located in the Boot ROM
(Bootstrap Mode). The default values of the special function registers (SFR) to which they are
forced during reset are listed in table 3-4 and 3-5 of chapter 3.
After reset is internally accomplished the port latches of ports 0 to 6 are set to FFH. This leaves port
0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines
(ports 1 to 6 and 9) output a one (1). Ports 7 and 8, which are input-only ports, have no internal latch
and therefore the contents of the special function registers P7 and P8 depend on the levels applied
to ports 7 and 8.
The content of the internal RAM of the C509-L is not affected by a reset. After power-up the content
is undefined, while it remains unchanged during a reset it the power supply is not turned off.
Semiconductor Group
5-2
1997-10-01