C509-L_97 Datasheet, PDF (221/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Fail Save Mechanisms
C509-L
8.1.2 Watchdog Timer Control Flags
The watchdog timer is controlled by two control flags (located in SFR IEN0 and IEN1) and one
status flags (located in SFR IP0).
Special Function Register IEN0 (Address A8H)
Special Function Register IEN1 (Address B8H)
Special Function Register IP0 (Address A9H)
Reset Value : 00H
Reset Value : 00H
Reset Value : 00H
Bit No.
A8H
MSB
AFH
EAL
AEH
WDT
ADH
ET2
ACH
ES0
ABH
ET1
AAH
EX1
A9H
ET0
LSB
A8H
EX0
IEN0
BFH BEH
B8H EXEN2 SWDT
BDH
EX6
BCH
EX5
BBH
EX4
BA2H B91H B8H
EX3 EX2 EADC
IEN1
7
6
5
4
3
2
1
0
A9H OWDS WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 IP0
Bit
WDT
SWDT
WDTS
The shaded bits are not used in controlling the watchdog timer.
Function
Watchdog timer refresh flag
Set to initiate a refresh of the watchdog timer. Must be set directly before
SWDT is set to prevent an unintentional refresh of the watchdog timer.
Watchdog timer start flag
Set to activate the watchdog timer. When directly set after setting WDT,
a watchdog timer refresh is performed.
Watchdog timer status flag
Set by hardware when a watchdog timer reset occurred.
Can be cleared or set by software
Semiconductor Group
8-3
1997-10-01