C509-L_97 Datasheet, PDF (178/290 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C509-L
6.5.3.3 Mode 2, 9-Bit UART (Serial Interface 0)
Mode 2 is functionally identical to mode 3 (see below). The only exception is, that in mode 2 the
baud rate can be programmed to two fixed quantities: either 1/16 or 1/32 of the oscillator frequency.
Note that serial interface 0 cannot achieve this baud rate in mode 3. Its baud rate clock is generated
by timer 1, which is incremented by a rate of f_OSC/6. The dedicated baud rate generator of serial
interface 1 however is clocked by a f_OSC signal and so its maximum baud rate is f_OSC/16.
6.5.3.4 Mode 3 / Mode A, 9-Bit UART (Serial Interfaces 0 and 1)
Eleven bits are transmitted (through TXD0/TXD1), or received (through RXD0/RXD1): a start bit (0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data
bit (TB80/TB81) can be assigned the value of 0 or 1. On reception the 9th data bit goes into
RB80/RB81 in S0CON/S1CON. Mode 3 may have a variable baud rate generated from either timer
1 or 2 depending on the state of TCLK and RCLK in SFR T2CON.
Figure 6-45a shows a simplified functional diagram of the both serial channels in mode 2 an 3 or
mode A, respectively. The associated timing is illustrated in figure 6-46b. The receive portion is
exactly the same as in mode 1. The transmit portion differs from mode 1 only in the 9th bit of the
transmit shift register.
Transmission is initiated by any instruction that uses S0BUF/S1BUF as a destination register. The
“write to S0BUF/S1BUF” signal also loads TB80/TB81 into the 9th bit position of the transmit shift
register and flags the TX control unit that a transmission is requested. Transmission commences at
S1P1 of the machine cycle following the next rollover in the divide-by-16 counter (thus the bit times
are synchronized to the divide-by-16 counter, and not to the “write-to-S0BUF/S1BUF” signal).
The transmission begins with the activation of SEND, which puts the start bit to TXD0/TXD1. One
bit time later, DATA is activated which enables the output bit of transmit shift register to TXD0/TXD1.
The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th
bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data shift out to the
right, zeros are clocked in from the left. When TB80/TB81 is at the output position of the shift
register, then the stop bit is just left of the TB80/TB81, and all positions to the left of that contain
zeros.
This condition flags the TX control unit to do one last shift and then deactivate SEND and set
TI0/TI1. This occurs at the 11th divide-by-16 rollover after “write-to-S0BUF/S1BUF”.
Reception is initiated by a detected 1-to-0 transition at RXD0/RXD1. For this purpose RXD0/RXD1
is sampled of a rate of 16 times whatever baud rate has been established. When a transition is
detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift
register.
At the 7th, 8th and 9th counter state of each bit time, the bit detector samples the value of
RxD0/RxD1. The value accepted is the value that was seen in at least 2 of the 3 samples. lf the
value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back
to looking for another 1-to-0 transition. lf the start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
As data bits come from the right, 1’s shift out to the left. When the start bit arrives at the leftmost
position in the shift register (which is a 9-bit register), it flags the RX control block to do one last shift,
load S0BUF/S1BUF and RB80/ RB81, and set RI0/RI1. The signal to load S0BUF/S1BUF and
Semiconductor Group
6-100
1997-10-01