MC908AZ60ACFUER Datasheet, PDF (77/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Functional Description
6.4.5.3 EEPROM-1 Erasing
The programmed state of an EEPROM bit is logic 0. Erasing changes the state to a logic 1. Only
EEPROM-1 bytes in the non-protected blocks and the EE1NVR register can be erased.
Use the following procedure to erase a byte, block or the entire EEPROM-1 array:
1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set EELAT in EE1CR.^(A)
NOTE
If using the AUTO mode, also set the AUTO bit in Step 1.
2. Byte erase: write any data to the desired address.^(B)
Block erase: write any data to an address within the desired block.^(B)
Bulk erase: write any data to an address within the array.^(B)
3. Set the EEPGM bit.^(C) Go to Step 7 if AUTO is set.
4. Wait for a time: t_EEBYTE for byte erase; t_EEBLOCK for block erase; t_EEBULK. for bulk erase.
5. Clear EEPGM bit.
6. Wait for a time, t_EEFPV, for the erasing voltage to fall. Go to Step 8.
7. Poll the EEPGM bit until it is cleared by the internal timer.^(D)
8. Clear EELAT bits.^(E)
NOTE
A. Setting the EELAT bit configures the address and data buses to latch
data for erasing the array. Only valid EEPROM-1 addresses will be latched.
If EELAT is set, other writes to the EE1CR will be allowed after a valid
EEPROM-1 write.
B. If more than one valid EEPROM write occurs, the last address and data
will be latched overriding the previous address and data. Once data is
written to the desired address, do not read EEPROM-1 locations other than
the written location. (Reading an EEPROM location returns the latched data
and causes the read address to be latched).
C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-valid
EEPROM address is latched. This is to ensure proper programming
sequence. Once EEPGM is set, do not read any EEPROM-1 locations;
otherwise, the current program cycle will be unsuccessful. When EEPGM
is set, the on-board programming sequence will be activated.
D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than t_EEBYTE /t_EEBLOCK/t_EEBULK. However, on other MCUs, this delay time
may be different. For forward compatibility, software should not make any
dependency on this delay time.
E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of high
voltage from the EEPROM-1 array.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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