MC908AZ60ACFUER Datasheet, PDF (315/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA
channel 0 registers (TACH0H–TACH0L) initially control the buffered PWM output. TIMA status control
register 0 (TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA
channel 2 registers (TACH2H–TACH2L) initially control the buffered PWM output. TIMA status control
register 2 (TASC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority
over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered PWM operation. The TIMA
channel 4 registers (TACH4H–TACH4L) initially control the buffered PWM output. TIMA status control
register 4 (TASC4) controls and monitors the PWM signal from the linked channels. MS4B takes priority
over MS4A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output (see 25.8.4 TIMA Channel Status and Control Registers).
25.4 Interrupts
The following TIMA sources can generate interrupt requests:
• TIMA overflow flag (TOF) — The TOF bit is set when the TIMA counter reaches the modulo value
programmed in the TIMA counter modulo registers. The TIMA overflow interrupt enable bit, TOIE,
enables TIMA overflow CPU interrupt requests. TOF and TOIE are in the TIMA status and control
register.
• TIMA channel flags (CH5F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
25.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
25.5.1 Wait Mode
The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are
not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of
wait mode.
If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA
before executing the WAIT instruction.
25.5.2 Stop Mode
The TIMA is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop
mode.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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