MC908AZ60ACFUER Datasheet, PDF (129/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Functional Description
Register Name
Read:
PLL Control Register (PCTL) Write:
Reset:
Read:
PLL Bandwidth Control Register (PB-
WC)
Write:
Reset:
Read:
PLL Programming Register (PPG) Write:
Reset:
Bit 7
PLLIE
0
AUTO
0
MUL7
0
6
5
PLLF
PLLON
0
1
LOCK
ACQ
0
0
MUL6
MUL5
1
1
= Unimplemented
4
BCS
0
XLD
0
MUL4
0
3
1
1
0
0
VRS7
0
Figure 10-2. I/O Register Summary
2
1
1
0
0
VRS6
1
1
1
1
0
0
VRS5
1
Bit 0
1
1
0
0
VRS4
0
Table 10-1. I/O Register Address Summary
Register
Address
PCTL
$001C
PBWC
$001D
PPG
$001E
10.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components.
An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the
external clock to the OSC1 pin and let the OSC2 pin float.
10.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
129