MC908AZ60ACFUER Datasheet, PDF (353/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

BDLC CPU Interface
27.5.5.5 Summary
Table 27-1. BDLC J1850 Bus Error Summary
Error Condition
Transmission Error
Cyclical Redundancy Check (CRC)
Error
Invalid Symbol: BDLC Receives
Invalid Bits (Noise)
Framing Error
Bus Short to V_DD
Bus Short to GND
BDLC Receives BREAK Symbol.
BDLC Function
For invalid bits or framing symbols on non-byte
boundaries, invalid symbol interrupt will be
generated. BDLC stops transmission.
CRC error interrupt will be generated. The BDLC will
wait for SOF.
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated.
Invalid symbol interrupt will be generated. The BDLC
will wait for start-of-frame (SOF).
The BDLC will not transmit until the bus is idle.
Thermal overload will shut down physical interface.
Fault condition is reflected in BSVR as an invalid
symbol.
The BDLC will wait for the next valid SOF. Invalid
symbol interrupt will be generated.
27.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and consists of five user
registers.
• BDLC analog and roundtrip delay register (BARD)
• BDLC control register 1 (BCR1)
• BDLC control register 2 (BCR2)
• BDLC state vector register (BSVR)
• BDLC data register (BDR)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 27-14. BDLC Block Diagram
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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