MC908AZ60ACFUER Datasheet, PDF (149/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Chapter 13
Break Module (BRK)
13.1 Introduction
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
13.2 Features
• Accessible I/O Registers during Break Interrupts
• CPU-Generated Break Interrupts
• Software-Generated Break Interrupts
• COP Disabling during Break Interrupts
13.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the MCU to normal operation. Figure 13-1 shows the
structure of the break module.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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