MC908AZ60ACFUER Datasheet, PDF (259/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Port E
TACH[1:0] — Timer Channel I/O Bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIM input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0 pins are timer channel
I/O pins or general-purpose I/O pins. (See 25.8.4 TIMA Channel Status and Control Registers).
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the TIM. However, the DDRE bits always
determine whether reading port E returns the states of the latches or the
states of the pins. (See Table 22-5).
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. (See
18.8.1 SCI Control Register 1).
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. (See
18.8.1 SCI Control Register 1).
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. (See Table 22-5).
22.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$000C
Bit 7
6
5
4
3
2
1
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1
0
0
0
0
0
0
0
Figure 22-15. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
259