MC908AZ60ACFUER Datasheet, PDF (112/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
CLOCK
CONTROL
CLOCK GENERATORS
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 9-1. SIM Block Diagram
Register Name
Bit 7
6
5
4
3
2
SIM Break Status Register (SBSR) R
R
R
R
R
R
SIM Reset Status Register (SRSR) POR
PIN
COP
ILOP
ILAD
0
SIM Break Flag Control Register (SBFCR) BCFE
R
R
R
R
R
1
Bit 0
BW
R
LVI
0
R
R
R = Reserved
Figure 9-2. SIM I/O Register Summary
Table 9-1. I/O Register Address Summary
Register
Address
SBSR
$FE00
SRSR
$FE01
SBFCR
$FE03
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
112
Freescale Semiconductor