MC908AZ60ACFUER Datasheet, PDF (369/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Electrical Specifications
28.1.7 5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing
Num⁽¹⁾
Characteristic⁽²⁾
Symbol
Min
Max
Unit
Operating Frequency⁽³⁾
Master
Slave
f_BUS(M)
f_BUS(S)
f_BUS/128
dc
f_BUS/2
f_BUS
MHz
Cycle Time
1
Master
Slave
2 Enable Lead Time
3 Enable Lag Time
t_cyc(M)
2
128
t_cyc
t_cyc(S)
1
—
t_Lead
15
—
ns
t_Lag
15
—
ns
Clock (SCK) High Time
4
Master
Slave
t_W(SCKH)M
100
—
ns
t_W(SCKH)S
50
—
Clock (SCK) Low Time
5
Master
Slave
t_W(SCKL)M
100
—
ns
t_W(SCKL)S
50
—
Data Setup Time (Inputs)
6
Master
Slave
t_SU(M)
45
t_SU(S)
5
—
ns
—
Data Hold Time (Inputs)
7
Master
Slave
Access Time, Slave⁽⁴⁾
8 ^{CPHA = 0}
CPHA = 1
9 Slave Disable Time (Hold Time to High-Impedance State)
Enable Edge Lead Time to Data Valid⁽⁵⁾
10
Master
Slave
t_H(M)
0
t_H(S)
15
t_A(CP0)
0
t_A(CP1)
0
t_DIS
—
t_EV(M)
—
t_EV(S)
—
—
ns
—
40
ns
20
25
ns
10
ns
40
Data Hold Time (Outputs, after Enable Edge)
11
Master
Slave
12
Data Valid
Master (Before Capture Edge)
t_HO(M)
0
t_HO(S)
5
t_V(M)
90
—
ns
—
—
ns
13
Data Hold Time (Outputs)
Master (Before Capture Edge)
t_HO(M)
100
—
ns
1. Item numbers refer to dimensions in Figure 28-1 and Figure 28-2.
2. All timing is shown with respect to 30% V_DD and 70% V_DD, unless otherwise noted; assumes 100 pF load on all SPI pins.
3. f_BUS = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state.
5. With 100 pF on all SPI pins.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
369