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Timer Interface Module B (TIMB)
20.4 Interrupts
The following TIMB sources can generate interrupt requests:
• TIMB overflow flag (TOF) — The TOF bit is set when the TIMB counter value reaches the modulo
value programmed in the TIMB counter modulo registers. The TIMB overflow interrupt enable bit,
TOIE, enables TIMB overflow CPU interrupt requests. TOF and TOIE are in the TIMB status and
control register.
• TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
20.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
20.5.1 Wait Mode
The TIMB remains active after the execution of a WAIT instruction. In wait mode, the TIMB registers are
not accessible by the CPU. Any enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
If TIMB functions are not required during wait mode, reduce power consumption by stopping the TIMB
before executing the WAIT instruction.
20.5.2 Stop Mode
The TIMB is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIMB counter. TIMB operation resumes when the MCU exits stop
mode.
20.6 TIMB During Break Interrupts
A break interrupt stops the TIMB counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see 9.7.3 SIM Break Flag Control Register).
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
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