MC908AZ60ACFUER Datasheet, PDF (373/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Electrical Specifications
28.1.10 CGM Acquisition/Lock Time Information
Description⁽¹⁾
Symbol
Min
Typ⁽²⁾
Max⁽²⁾
Unit
Notes
Manual Mode Time to Stable
t_ACQ
Manual Stable to Lock Time
Manual Acquisition Time
Tracking Mode Entry Frequency
Tolerance
t_AL
t_LOCK
D_TRK
—
(8 x V_DDA) /
(f_CGMXCLK x K_ACQ)
—
s ^{If CF Chosen}
Correctly
—
(4 x V_DDA) /
(f_CGMXCLK x K_TRK)
—
s ^{If CF Chosen}
Correctly
—
t_ACQ+t_AL
—
s
0
—
± 3.6
%
Acquisition Mode Entry
Frequency Tolerance
D_UNT
± 6.3
—
± 7.2
%
LOCK Entry Freq. Tolerance
LOCK Exit Freq. Tolerance
Reference Cycles per
Acquisition Mode Measurement
D_LOCK
D_UNL
n_ACQ
0
± 0.9
—
—
± 0.9
%
—
± 1.8
%
32
—
—
Reference Cycles per Tracking
Mode Measurement
n_TRK
—
128
—
—
Automatic Mode Time to Stable
Automatic Stable to Lock Time
Automatic Lock Time
PLL Jitter, Deviation of Average
Bus Frequency over 2 ms⁽³⁾
t_ACQ
t_AL
t_LOCK
n_ACQ/f_XCLK
n_TRK/f_XCLK
—
0
(8 x V_DDA) /
(f_XCLK x K_ACQ)
(4 x V_DDA) /
(f_XCLK x K_TRK)
0.65
—
—
25
± (f_CRYS)
x (.025%)
x (N/4)
s ^{If CF Chosen}
Correctly
s ^{If CF Chosen}
Correctly
ms
%
N = VCO Freq.
Mult.
K value for automatic mode
time to stable
K_acq
—
0.2
—
—
K value
K_trk
—
0.004
—
—
1. V_DD = 5.0 Vdc ± 0.5 V, V_SS = 0 Vdc, T_A = –40°C to T_A (MAX), unless otherwise noted.
2. Conditions for typical and maximum values are for Run mode with f_CGMXCLK = 8 MHz, f_BUSDES = 8 MHz, N = 4, L = 7, discharged C_F = 15 nF,
V_DD = 5 Vdc.
3. Guaranteed by not tested. Refer to Chapter 10 Clock Generator Module (CGM) for guidance on the use of the PLL.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
373