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Low-Power Modes
The BDR is double buffered via a transmit shadow register and a receive shadow register. After the byte
in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register
is loaded into the transmit shift register. Once the transmit shift register has shifted the first bit out, the
TDRE flag is set, and the shadow register is ready to accept the next data byte. The receive shadow
register works similarly. Once a complete byte has been received, the receive shift register stores the
newly received byte into the receive shadow register. The RDRF flag is set to indicate that a new byte of
data has been received. The programmer has one BDLC byte reception time to read the shadow register
and clear the RDRF flag before the shadow register is overwritten by the newly received byte.
To abort an in-progress transmission, the programmer should stop loading data into the BDR. This will
cause a transmitter underrun error and the BDLC automatically will disable the transmitter on the next
non-byte boundary. This means that the earliest a transmission can be halted is after at least one byte
plus two extra logic 1s have been transmitted. The receiver will pick this up as an error and relay it in the
state vector register as an invalid symbol error.
NOTE
The extra logic 1s are an enhancement to the J1850 protocol which forces a byte boundary condition fault.
This is helpful in preventing noise from going onto the J1850 bus from a corrupted message.
27.7 Low-Power Modes
The following information concerns wait mode and stop mode.
27.7.1 Wait Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
WAIT instruction and the WCM bit in BDLC control register 1 (BCR1) is previously clear. In BDLC wait
mode, the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in progress at the time that this mode
is entered, will cause the BDLC to wake up and generate a CPU interrupt request if the interrupt enable
(IE) bit in the BDLC control register 1 (BCR1) is previously set. (See 27.6.2 BDLC Control Register 1 for
a better understanding of IE.) This results in less of a power saving, but the BDLC is guaranteed to receive
correctly the message which woke it up, since the BDLC internal operating clocks are kept running.
NOTE
Ensuring that all transmissions are complete or aborted before putting the
BDLC into wait mode is important.
27.7.2 Stop Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BDLC control register
1 (BCR1) is previously set. This is the lowest power mode that the BDLC can enter.
A subsequent passive-to-active transition on the J1850 bus will cause the BDLC to wake up and generate
a non-maskable CPU interrupt request. When a STOP instruction is used to put the BDLC in stop mode,
the BDLC is not guaranteed to correctly receive the message which woke it up, since it may take some
time for the BDLC internal operating clocks to restart and stabilize. If a WAIT instruction is used to put the
BDLC in stop mode, the BDLC is guaranteed to correctly receive the byte which woke it up, if and only if
an end-of-frame (EOF) has been detected prior to issuing the WAIT instruction by the CPU. Otherwise,
the BDLC will not correctly receive the byte that woke it up.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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