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Reset and System Initialization
9.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see Figure 9-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
or POR (see Figure 9-6). Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the
falling edge of RST shown in Figure 9-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
IRST
RST
CGMXCLK
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
IAB
VECTOR HIGH
Figure 9-5. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 9-6. Sources of Internal Reset
Table 9-3. PIN Bit Set Timing
Reset Recovery Type
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
115