MC908AZ60ACFUER Datasheet, PDF (254/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Input/Output Ports
22.4 Port C
Port C is an 6-bit general-purpose bidirectional I/O port. Note that PTC5 is only available on 64-pin
package options.
22.4.1 Port C Data Register
The port C data register contains a data latch for each of the six port C pins.
Address:
Read:
Write:
Reset:
Alternative
Functions:
$0002
Bit 7
0
R
R
6
5
0
PTC5
R
= Reserved
4
3
PTC4
PTC3
Unaffected by Reset
2
PTC2
MCLK
Figure 22-8. Port C Data Register (PTC)
1
PTC1
Bit 0
PTC0
PTC[5:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data (5:0).
MCLK — System Clock Bit
The system clock is driven out of PTC2 when enabled by MCLKEN bit in PTCDDR7.
22.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006
Bit 7
6
Read:
0
MCLKEN
Write:
R
5
DDRC5
4
DDRC4
3
DDRC3
2
DDRC2
1
DDRC1
Reset: 0
0
0
0
0
0
0
R
= Reserved
Figure 22-9. Data Direction Register C (DDRC)
Bit 0
DDRC0
0
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, DDRC2 has no
effect. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
254
Freescale Semiconductor