MC908AZ60ACFUER Datasheet, PDF (339/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

BDLC MUX Interface
27.4 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol
handler and the physical interface.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 27-4. BDLC Block Diagram
27.4.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to remove narrow noise pulses from the
incoming message. An outline of the digital filter is shown in Figure 27-5.
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRXD)
INPUT
SYNC
DQ
4-BIT UP/DOWN COUTER
UP/DOWN
OUT
DATA
LATCH
DQ
FILTERED
RX DATA OUT
MUX INTERFACE
CLOCK
Figure 27-5. BDLC Rx Digital Filter Block Diagram
27.4.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see f_BDLC parameter in Table 27-3).
At each positive edge of the clock signal, the current state of the receiver physical interface (BDRxD)
signal is sampled. The BDRxD signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
339