MC908AZ60ACFUER Datasheet, PDF (279/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

CGMXCLK
OSC
CGM
MSCAN08
÷2
PLL
CLKSRC
Clock System
÷2
CGMOUT
(TO SIM)
BCS
÷2
(2 * BUS FREQ.)
PRESCALER
(1 .. 64)
MSCANCLK
Figure 23-7. Clocking Scheme
The clock source bit (CLKSRC) in the MSCAN08 module control register (CMCR1) (see 23.13.1
MSCAN08 Module Control Register 0) defines whether the MSCAN08 is connected to the output of the
crystal oscillator or to the PLL output.
The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of
the CAN protocol are met.
NOTE
If the system clock is generated from a PLL, it is recommended to select the
crystal clock source rather than the system clock source due to jitter
considerations, especially at faster CAN bus rates.
A programmable prescaler is used to generate out of the MSCAN08 clock the time quanta (Tq) clock. A
time quantum is the atomic unit of time handled by the MSCAN08.
f_Tq =
f_MSCANCLK
Presc value
A bit time is subdivided into three segments⁽¹⁾ (see Figure 23-8).
• SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to
happen within this section.
• Time segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN
standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.
1. For further explanation of the underlying concepts please refer to ISO/DIS 11 519-1, Section 10.3.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
279