MC908AZ60ACFUER Datasheet, PDF (201/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

I/O Registers
18.8.6 SCI Data Register
The SCI data register is the buffer between the internal data bus and the receive and transmit shift
registers. Reset has no effect on data in the SCI data register.
Address: $0018
Bit 7
6
5
4
3
2
1
Bit 0
Read: R7
R6
R5
R4
R3
R2
R1
R0
Write: T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by Reset
Figure 18-17. SCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018
writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.
NOTE
Do not use read-modify-write instructions on the SCI data register.
18.8.7 SCI Baud Rate Register
The baud rate register selects the baud rate for both the receiver and the transmitter.
Address:
Read:
Write:
Reset:
$0019
Bit 7
6
5
4
3
2
1
0
0
SCP1
SCP0
R
SCR2
SCR1
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 18-18. SCI Baud Rate Register (SCBR)
Bit 0
SCR0
0
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in Table 18-9. Reset clears SCP1
and SCP0.
Table 18-9. SCI Baud Rate Prescaling
SCP[1:0]
00
01
10
11
Prescaler Divisor (PD)
1
3
4
13
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in Table 18-10. Reset clears
SCR2–SCR0.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
201