MC908AZ60ACFUER Datasheet, PDF (212/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Serial Peripheral Interface (SPI)
delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR
and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32
MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
BUS
CLOCK
WRITE
TO SPDR
INITIATION DELAY
MOSI
SCK
CPHA = 1
SCK
CPHA = 0
SCK CYCLE
NUMBER
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
BUS
CLOCK
WRITE
TO SPDR
BUS
CLOCK
EARLIEST LATEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
EARLIEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
Figure 19-6. Transmission Start Delay (Master)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
212
Freescale Semiconductor