MC908AZ60ACFUER Datasheet, PDF (296/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

MSCAN Controller (MSCAN08)
23.13.9 MSCAN08 Identifier Acceptance Control Register
Address: $0508
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
0
IDAM1 IDAM0
0
IDHIT1 IDHIT0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 23-23. Identifier Acceptance Control Register (CIDAC)
IDAM1–IDAM0— Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter organization (see 23.5 Identifier
Acceptance Filter). Table 23-9 summarizes the different settings. In “filter closed” mode no messages
will be accepted so that the foreground buffer will never be reloaded.
Table 23-9. Identifier Acceptance Mode Settings
IDAM1
0
0
1
1
IDAM0
0
1
0
1
Identifier Acceptance Mode
Single 32-Bit Acceptance Filter
Two 16-Bit Acceptance Filter
Four 8-Bit Acceptance Filters
Filter Closed
IDHIT1–IDHIT0— Identifier Acceptance Hit Indicator
The MSCAN08 sets these flags to indicate an identifier acceptance hit (see 23.5 Identifier Acceptance
Filter). Table 23-9 summarizes the different settings.
Table 23-10. Identifier Acceptance Hit Indication
IDHIT1
0
0
1
1
IDHIT0
0
1
0
1
Identifier Acceptance Hit
Filter 0 Hit
Filter 1 Hit
Filter 2 Hit
Filter 3 Hit
The IDHIT indicators are always related to the message in the foreground buffer. When a message gets
copied from the background to the foreground buffer, the indicators are updated as well.
NOTE
The CIDAC register can be written only if the SFTRES bit in the CMCR0 is
set.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
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