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Monitor ROM (MON)
14.3.7 MC68HC908AZ60A Baud Rate
The MC68HC908AZ60A features a monitor mode which is optimised to operate with either a 4.9152 MHz
crystal clock source (or multiples of 4.9152 MHz) or a 4 MHz crystal (or multiples of 4 MHz). This supports
designs which use the MSCAN module, which is generally clocked from a 4 MHz, 8 MHz or 16 MHZ
internal reference clock. The table below outlines the available baud rates for a range of crystals and how
they can match to a PC baud rate.
Table 14-10 MC68HC908AZ60A Monitor Baud Rate Selection
Clock freq
32kHz
1MHz
2MHz
4MHz
4.194MHz
4.9152MHz
8MHz
16MHz
Baud rate
PTC3=0 PTC3=1
57.97
28.98
1811.59
905.80
3623.19 1811.59
7246.37 3623.19
7597.83 3798.91
8904.35 4452.17
14492.72 7246.37
28985.51 14492.75
Closest PC baud PC
PTC3=0 PTC3=1
57.6
28.8
1800
900
3600
1800
7200
3600
7680
3840
8861
4430
14400
7200
28800
14400
Error %
PTC3=0 PTC3=1
0.64
0.63
0.64
0.64
0.64
0.64
0.64
0.64
1.08
1.08
0.49
0.50
0.64
0.64
0.64
0.64
WARNING
Care should be taken when setting the baud rate since incorrect baud
rate setting can result in communications failure.
14.3.8 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors. If FLASH is
unprogrammed, the eight security byte values to be sent are $FF, the
unprogrammed state of FLASH.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PA0.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
160
Freescale Semiconductor