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Table 8-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
INH
INH
IX1
SP1
IX
INH
INH
IMM
DIR
EXT
IX2
SP2
IX1
SP1
IX
MSB
LSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
1
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
2
3
3
4
BRA NEG
2 REL 2 DIR
3
5
BRN CBEQ
2 REL 3 DIR
3
BHI
2 REL
3
4
BLS COM
2 REL 2 DIR
3
4
BCC LSR
2 REL 2 DIR
3
4
BCS STHX
2 REL 2 DIR
3
4
BNE ROR
2 REL 2 DIR
3
4
BEQ ASR
2 REL 2 DIR
3
4
BHCC LSL
2 REL 2 DIR
3
4
BHCS ROL
2 REL 2 DIR
3
4
BPL DEC
2 REL 2 DIR
3
5
BMI DBNZ
2 REL 3 DIR
3
4
BMC
INC
2 REL 2 DIR
3
3
BMS TST
2 REL 2 DIR
3
BIL
2 REL
3
3
BIH
CLR
2 REL 2 DIR
4
5
6
9E6
7
1
1
4
5
3
NEGA NEGX NEG NEG NEG
1 INH 1 INH 2 IX1 3 SP1 1 IX
4
4
5
6
4
CBEQA CBEQX CBEQ CBEQ CBEQ
3 IMM 3 IMM 3 IX1+ 4 SP1 2 IX+
5
7
3
MUL
DIV
NSA
1 INH 1 INH 1 INH
2
DAA
1 INH
1
1
4
5
3
COMA COMX COM COM COM
1 INH 1 INH 2 IX1 3 SP1 1 IX
1
1
4
5
3
LSRA LSRX LSR
LSR
LSR
1 INH 1 INH 2 IX1 3 SP1 1 IX
3
4
3
LDHX LDHX CPHX
3 IMM 2 DIR 3 IMM
4
CPHX
2 DIR
1
1
4
5
3
RORA RORX ROR ROR ROR
1 INH 1 INH 2 IX1 3 SP1 1 IX
1
1
4
5
3
ASRA ASRX ASR ASR ASR
1 INH 1 INH 2 IX1 3 SP1 1 IX
1
1
4
5
3
LSLA LSLX LSL
LSL
LSL
1 INH 1 INH 2 IX1 3 SP1 1 IX
1
1
4
5
3
ROLA ROLX ROL ROL ROL
1 INH 1 INH 2 IX1 3 SP1 1 IX
1
1
4
5
3
DECA DECX DEC DEC DEC
1 INH 1 INH 2 IX1 3 SP1 1 IX
3
3
5
6
4
DBNZA DBNZX DBNZ DBNZ DBNZ
2 INH 2 INH 3 IX1 4 SP1 2 IX
1
1
4
5
3
INCA INCX INC
INC
INC
1 INH 1 INH 2 IX1 3 SP1 1 IX
1
1
3
4
2
TSTA TSTX TST
TST
TST
1 INH 1 INH 2 IX1 3 SP1 1 IX
5
4
4
MOV MOV MOV
3 DD 2 DIX+ 3 IMD
4
MOV
2 IX+D
1
1
3
4
2
CLRA CLRX CLR CLR CLR
1 INH 1 INH 2 IX1 3 SP1 1 IX
8
7
RTI
1 INH
4
RTS
1 INH
9
SWI
1 INH
2
TAP
1 INH
1
TPA
1 INH
2
PULA
1 INH
2
PSHA
1 INH
2
PULX
1 INH
2
PSHX
1 INH
2
PULH
1 INH
2
PSHH
1 INH
1
CLRH
1 INH
1
STOP
1 INH
1
WAIT
1 INH
9
A
B
3
2
3
BGE SUB SUB
2 REL 2 IMM 2 DIR
3
2
3
BLT
CMP CMP
2 REL 2 IMM 2 DIR
3
2
3
BGT SBC SBC
2 REL 2 IMM 2 DIR
3
2
3
BLE CPX CPX
2 REL 2 IMM 2 DIR
2
2
3
TXS AND AND
1 INH 2 IMM 2 DIR
2
2
3
TSX
BIT
BIT
1 INH 2 IMM 2 DIR
2
3
LDA
LDA
2 IMM 2 DIR
1
2
3
TAX
AIS
STA
1 INH 2 IMM 2 DIR
1
2
3
CLC EOR EOR
1 INH 2 IMM 2 DIR
1
2
3
SEC ADC ADC
1 INH 2 IMM 2 DIR
2
2
3
CLI
ORA ORA
1 INH 2 IMM 2 DIR
2
2
3
SEI
ADD ADD
1 INH 2 IMM 2 DIR
1
RSP
1 INH
2
JMP
2 DIR
1
4
4
NOP BSR
JSR
1 INH 2 REL 2 DIR
2
3
*
LDX
LDX
2 IMM 2 DIR
1
2
3
TXA
AIX
STX
1 INH 2 IMM 2 DIR
C
D
4
4
SUB SUB
3 EXT 3 IX2
4
4
CMP CMP
3 EXT 3 IX2
4
4
SBC SBC
3 EXT 3 IX2
4
4
CPX CPX
3 EXT 3 IX2
4
4
AND AND
3 EXT 3 IX2
4
4
BIT
BIT
3 EXT 3 IX2
4
4
LDA
LDA
3 EXT 3 IX2
4
4
STA
STA
3 EXT 3 IX2
4
4
EOR EOR
3 EXT 3 IX2
4
4
ADC ADC
3 EXT 3 IX2
4
4
ORA ORA
3 EXT 3 IX2
4
4
ADD ADD
3 EXT 3 IX2
3
4
JMP JMP
3 EXT 3 IX2
5
6
JSR
JSR
3 EXT 3 IX2
4
4
LDX
LDX
3 EXT 3 IX2
4
4
STX
STX
3 EXT 3 IX2
9ED
E
5
3
SUB SUB
4 SP2 2 IX1
5
3
CMP CMP
4 SP2 2 IX1
5
3
SBC SBC
4 SP2 2 IX1
5
3
CPX CPX
4 SP2 2 IX1
5
3
AND AND
4 SP2 2 IX1
5
3
BIT
BIT
4 SP2 2 IX1
5
3
LDA
LDA
4 SP2 2 IX1
5
3
STA
STA
4 SP2 2 IX1
5
3
EOR EOR
4 SP2 2 IX1
5
3
ADC ADC
4 SP2 2 IX1
5
3
ORA ORA
4 SP2 2 IX1
5
3
ADD ADD
4 SP2 2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
9EE
F
4
2
SUB SUB
3 SP1 1 IX
4
2
CMP CMP
3 SP1 1 IX
4
2
SBC SBC
3 SP1 1 IX
4
2
CPX CPX
3 SP1 1 IX
4
2
AND AND
3 SP1 1 IX
4
2
BIT
BIT
3 SP1 1 IX
4
2
LDA
LDA
3 SP1 1 IX
4
2
STA
STA
3 SP1 1 IX
4
2
EOR EOR
3 SP1 1 IX
4
2
ADC ADC
3 SP1 1 IX
4
2
ORA ORA
3 SP1 1 IX
4
2
ADD ADD
3 SP1 1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
INH Inherent
REL Relative
IMM Immediate
IX Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
Low Byte of Opcode in Hexadecimal
MSB
LSB
0
0 High Byte of Opcode in Hexadecimal
5 Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode