MC908AZ60ACFUER Datasheet, PDF (113/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

SIM Bus Clock Control and Generation
Table 9-2 shows the internal signal names used in this chapter.
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Table 9-2. Signal Name Conventions
Description
Buffered Version of OSC1 from Clock Generator Module (CGM)
PLL Output
PLL-Based or OSC1-Based Clock Output from CGM Module
(Bus Clock = CGMOUT Divided by Two)
Internal Address Bus
Internal Data Bus
Signal from the Power-On Reset Module to the SIM
Internal Reset Signal
Read/Write Signal
9.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 9-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 10 Clock Generator Module
(CGM)).
OSC1
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 9-3. CGM Clock Signals
9.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four. (See Chapter 10 Clock Generator Module (CGM)).
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
113