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Appendix A
MC68HC908AS60 and MC68HC908AZ60
A.1 Changes from the MC68HC908AS60 and MC68HC908AZ60 (non-A suffix
devices)
A.1.1 Specification
Specifications for MC68HC908AS60A and MC68HC908AZ60A devices have been integrated, reflecting
the many commonalties.
A.1.2 FLASH
A.1.2.1 FLASH Architecture
FLASH-1 and FLASH-2 are made from a new nonvolatile memory (NVM) technology. The architecture is
now arranged in pages of 128 bytes and 2 rows per page. Programming is now carried out on a whole
row (64 bytes) at a time. Erasing is now carried out on a whole page (128 bytes) at a time. In this new
technology an erased bit now reads as a logic 1 and a programmed bit now reads as a logic 0.
A.1.2.2 FLASH Control Registers
FLASH-1 control register is moved from $FE0B to $FF88. FLASH-2 control register is moved from $FE11
to $FE08. Bits 4 to 7 in the FLASH control registers are no longer used since clock control is now achieved
automatically and erasing of variable block sizes is no longer a feature. Bit 2 of the FLASH control
registers no longer activates a so-called ‘margin read’ operation but instead is the bit that controls a mass
(bulk) erase operation.
A.1.2.3 FLASH Programming Procedure
Programming of the FLASH is largely as before within the new architecture constraints outlined above.
However, an extra dummy write operation to any address in the page is required prior to programming
data into one of the two rows in the page. Margin reading of programmed data is no longer required. Nor
is read / verify / re-pulse of the programming a requirement.
A.1.2.4 FLASH Programming Time
The most significant change resulting from the new FLASH technology is that the byte programming time
is reduced to a maximum of 40us. This represents several orders of magnitude improvement from the
previous technology.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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