MC908AZ60ACFUER Datasheet, PDF (169/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

LVI Status Register
16.4 LVI Status Register
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the LVI_TRIPF voltage for 32 to 40
CGMXCLK cycles. (See Table 16-1). Reset clears the LVIOUT bit.
Table 16-1. LVIOUT Bit Indication
V_DD
At Level:
V_DD > LVI_TRIPR
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD < LVI_TRIPR
For Number of
CGMXCLK Cycles:
Any
< 32 CGMXCLK Cycles
Between 32 and 40
CGMXCLK Cycles
> 40 CGMXCLK Cycles
Any
LVIOUT
0
0
0 or 1
1
Previous Value
16.5 LVI Interrupts
The LVI module does not generate interrupt requests.
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.6.1 Wait Mode
With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT
instruction.
With the LVIRST bit in the configuration register programmed to 1, the LVI module can generate a reset
and bring the MCU out of wait mode.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
169