MC908AZ60ACFUER Datasheet, PDF (261/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

22.7.1 Port F Data Register
The port F data register contains a data latch for each of the seven port F pins.
Address:
Read:
Write:
Reset:
Alternative
Function:
$0009
Bit 7
0
R
R
6
5
4
3
2
PTF6
PTF5
PTF4
PTF3
PTF2
Unaffected by Reset
TBCH1 TBCH0 TACH5 TACH4
= Reserved
Figure 22-17. Port F Data Register (PTF)
1
PTF1
TACH3
Bit 0
PTF0
TACH2
Port F
PTF[6:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0].
TACH[5:2] — Timer A Channel I/O Bits
The PTF3–PTF0/TACH2 pins are the TIM input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTF3–PTF0/TACH2 pins are timer channel I/O pins or
general-purpose I/O pins. (See 25.8.1 TIMA Status and Control Register).
TBCH[1:0] — Timer B Channel I/O Bits
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0 pins are timer channel
I/O pins or general-purpose I/O pins. (See 20.8.1 TIMB Status and Control Register).
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 22-6).
22.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to
a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$000D
Bit 7
6
5
4
3
2
1
0
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1
R
0
0
0
0
0
0
0
R
= Reserved
Figure 22-18. Data Direction Register F (DDRF)
Bit 0
DDRF0
0
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
261