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14.3.1 Entering Monitor Mode
Table 14-1 shows the pin conditions for entering monitor mode.
Table 14-1. Mode Selection
Functional Description
Mode
CGMOUT
Bus
Frequency
V_HI⁽¹⁾
1 0 1 1 Monitor
C-----G----M-----X-----C----L---K--- _or C-----G----M-----V-----C----L---K---
2
2
C-----G----M------O----U----T---
2
V_HI⁽¹⁾
1 0 1 0 Monitor
CGMXCLK
C-----G----M------O----U----T---
2
1. For V_HI, 28.1.4 5.0 Volt DC Electrical Characteristics, and 28.1.1 Maximum Ratings.
Enter monitor mode by either
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes (see 14.3.8 Security). After the
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host computer, indicating
that it is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The alternate vectors are in the
$FE page instead of the $FF page and allow code execution from the internal monitor firmware instead
of user code. The COP module is disabled in monitor mode as long as V_HI (see 28.1.4 5.0 Volt DC
Electrical Characteristics), is applied to either the IRQ pin or the RESET pin. (See Chapter 9 System
Integration Module (SIM) for more information on modes of operation).
NOTE
Holding the PTC3 pin low when entering monitor mode causes a bypass of
a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to
the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at
maximum bus frequency.
Table 14-2 is a summary of the differences between user mode and monitor mode.
Table 14-2. Mode Differences
Modes
COP
Reset
Vector
High
Functions
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Monitor
Enabled
Disabled⁽¹⁾
$FFFE
$FEFE
$FFFF
$FEFF
$FFFC
$FEFC
$FFFD
$FEFD
$FFFC
$FEFC
$FFFD
$FEFD
1. If the high voltage (V_HI) is removed from the IRQ and/or RESET pin while in monitor mode,
the SIM asserts its COP enable output. The COP is enabled or disabled by the COPD bit
in the configuration register. (see 28.1.4 5.0 Volt DC Electrical Characteristics).
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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