MC908AZ60ACFUER Datasheet, PDF (161/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

V_DD
4096 + 32 CGMXCLK CYCLES
RST
24 BUS CYCLES (MINIMUM)
Functional Description
FROM HOST
PA0
FROM MCU
1
4
1
1
2
4
1
NOTE: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
4 = Wait 1 bit time before sending next byte.
Figure 14-6. Monitor Mode Entry Timing
If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and
can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on
reset occurs. After the host bypasses security, any reset other than a power-on reset requires the host to
send another eight bytes. If the reset was not a power-on reset, the security remains bypassed regardless
of the data that the host sends.
If the received bytes do not match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading FLASH locations returns undefined data,
and trying to execute code from FLASH causes an illegal address reset. After the host fails to bypass
security, any reset other than a power-on reset causes an endless loop of illegal address resets.
After receiving the eight security bytes from the host, the MCU transmits a break character signalling that
it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
161