MC908AZ60ACFUER Datasheet, PDF (350/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Byte Data Link Controller (BDLC)
27.5.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx shadow register, Rx shift
register, Tx shift register, and loopback multiplexer as shown in Figure 27-13.
BDRxD
TO PHYSICAL INTERFACE
BDTxD
DLOOP FROM BCR2
LOOPBACK CONTROL
LOOPBACK
MULTIPLEXER
STATE MACHINE
Rx SHIFT REGISTER
Rx SHADOW REGISTER
8
Tx SHIFT REGISTER
Tx SHADOW REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 27-13. BDLC Protocol Handler Outline
27.5.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus and makes them available in
parallel form to the Rx shadow register. The Tx shift register takes data, in parallel form, from the Tx
shadow register and presents it serially to the state machine so that it can be transmitted onto the J1850
bus.
27.5.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of data, this data is transferred to
the Rx shadow register and RDRF or RXIFR is set (see 27.6.4 BDLC State Vector Register) and an
interrupt is generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer takes place, this new
data byte in the Rx shadow register is available to the CPU interface, and the Rx shift register is ready to
shift in the next byte of data. Data in the Rx shadow register must be retrieved by the CPU before it is
overwritten by new data from the Rx shift register.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
350
Freescale Semiconductor