MC908AZ60ACFUER Datasheet, PDF (257/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Port D
22.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRD7
Write:
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
Reset: 0
0
0
0
0
0
0
0
Figure 22-12. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 22-13 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 22-13. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-4 summarizes the operation of the port D pins.
Table 22-4. Port D Pin Functions
DDRD PTD
Bit
Bit
I/O Pin
Mode
Accesses to DDRD
Read/Write
0
X
Input, Hi-Z
DDRD[7:0]
1
X
Output
DDRD[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Accesses to PTD
Read
Write
Pin
PTD[7:0]⁽¹⁾
PTD[7:0]
PTD[7:0]
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
257