MC908AZ60ACFUER Datasheet, PDF (256/414 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

Input/Output Ports
22.5 Port D
Port D is an 8-bit general-purpose I/O port. Note that PTD7 is only available on 64-pin package options.
22.5.1 Port D Data Register
Port D is a 8-bit special function port that shares seven of its pins with the analog to digital converter and
two with the timer interface modules.
Address:
Read:
Write:
Reset:
Alternative
Functions:
$0003
Bit 7
PTD7
6
5
4
3
2
PTD6
PTD5
PTD4
PTD3
PTD2
Unaffected by Reset
ATD14 ATD13 ATD12 ATD11 ATD10
TACLK
TBCLK
Figure 22-11. Port D Data Register (PTD)
1
PTD1
ATD9
Bit 0
PTD0
ATD8
PTD[7:0] — Port D Data Bits
PTD[7:0] are read/write, software programmable bits. Data direction of PTD[7:0] pins are under the
control of the corresponding bit in data direction register D.
ATD[14:8] — ADC Channel Status Bits
PTD6/ATD14/TACLK–PTD0/ATD8 are seven of the 15 analog-to-digital converter channels. The ADC
channel select bits, CH[4:0], determine whether the PTD6/ATD14/TACLK–PTD0/ATD8 pins are ADC
channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding
bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed
as an input. Otherwise, the data will reflect the value in the data latch. (See Chapter 26
Analog-to-Digital Converter (ADC)).
NOTE
Data direction register D (DDRD) does not affect the data direction of port
D pins that are being used by the TIMA or TIMB. However, the DDRD bits
always determine whether reading port D returns the states of the latches
or a 0.
TACLK/TBCLK — Timer Clock Input Bit
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA. The PTD4/ATD12/TBCLK pin is
the external clock input for the TIMB. The prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK
or PTD4/ATD12/TBCLK as the TIM clock input. (See 25.8.4 TIMA Channel Status and Control
Registers and 20.8.4 TIMB Channel Status and Control Registers). When not selected as the TIM
clock, PTD6/ATD14/TACLK and PTD4/ATD12/TBCLK are available for general-purpose I/O. While
TACLK/TBCLK are selected corresponding DDRD bits have no effect.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
256
Freescale Semiconductor