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Memory Map
2.3 Additional Status and Control Registers
Selected addresses in the range $FE00 to $FFCB contain additional Status and Control registers as
shown in Figure 2-3. A noted exception is the COP Control Register (COPCTL) at address $FFFF.
Addr.
Register Name
Bit 7
$FE00
SIM Break Status Register ^Read:
(SBSR) _Write:
R
$FE01
SIM Reset Status Register ^{Read: POR}
(SRSR) _Write:
$FE03
SIM Break Flag Control ^Read:
Register (SBFCR) _Write:
BCFE
$FE08
FLASH-2 Control Register ^Read:
(FL2CR) _Write:
0
$FE09
Configuration Write-Once
Register (CONFIG-2)
Read:
EEDIVCLK
Write:
$FE0C
Break Address Register High
(BRKH)
Read:
Write:
Bit 15
$FE0D
Break Address Register Low ^Read:
(BRKL) _Write:
Bit 7
$FE0E
Break Status and Control ^Read:
Register (BRKSCR) _Write:
BRKE
$FE0F
LVI Status Register ^{Read: LVIOUT}
(LVISR) _Write:
$FE10
EE1DIV Hi Nonvolatile Read: EEDIVS-
Register (EE1DIVHNVR) Write: ECD
6
R
PIN
R
0
R
14
6
BRKA
0
R
5
4
3
2
R
R
R
R
COP
ILOP
ILAD
0
R
R
R
R
0
0
HVEN VERF
AT60A
R
MSCAND
R
R
13
12
11
10
5
4
3
2
0
0
0
0
0
0
0
0
R
R
R
EEDIV10
$FE11
EE1DIV Lo Nonvolatile
Register (EE1DIVLNVR)
Read:
Write:
EEDIV7
$FE1A _{EE1DIV Divider High Register} Read: _EEDIVS-
(EE1DIVH) _Write: ECD
$FE1B
EE1DIV Divider Low Register
(EE1DIVL)
Read:
Write:
EEDIV7
$FE1C
EEPROM-1 Nonvolatile
Register (EE1NVR)
Read:
UNUSED
Write:
$FE1D
EEPROM-1 Control Register
(EE1CR)
Read:
UNUSED
Write:
EEDIV6 EEDIV5 EEDIV4 EEDIV3
0
0
0
0
EEDIV6 EEDIV5 EEDIV4 EEDIV3
UNUSED UNUSED EEPRTCT EEBP3
0
EEOFF EERAS1 EERAS0
EEDIV2
EEDIV10
EEDIV2
EEBP2
EELAT
1
BW
0
LVI
R
ERASE
R
9
1
0
0
EEDIV9
EEDIV1
EEDIV9
EEDIV1
EEBP1
AUTO
Bit 0
R
0
R
PGM
AZxx
Bit 8
Bit 0
0
0
EEDIV8
EEDIV0
EEDIV8
EEDIV0
EEBP0
EEPGM
= Unimplemented
R = Reserved
Figure 2-3. Additional Status and Control Registers (Sheet 1 of 2)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
44
Freescale Semiconductor