UM10430 Datasheet, PDF (983/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table 930. Register
Name
-
OUTCLK_3_CTRL
OUTCLK_4_CTRL
overview:
Access
-
R/W
R/W
CGU (base
Address
offset
0x050
0x054
0x058
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base clock BASE_M3_CLK
OUTCLK_5_CTRL R/W
0x05C
Output stage 5 control register for 0x0100 0000
base clock BASE_SPIFI_CLK
-
-
0x060 Reserved
-
OUTCLK_7_CTRL R/W
0x064
Output stage 7 control register for 0x0100 0000
base clock BASE_PHY_RX_CLK
OUTCLK_8_CTRL R/W
0x068
Output stage 8 control register for 0x0100 0000
base clock BASE_PHY_TX_CLK
OUTCLK_9_CTRL R/W
0x06C
Output stage 9 control register for 0x0100 0000
base clock BASE_APB1_CLK
OUTCLK_10_CTRL R/W
0x070
Output stage 10 control register for 0x0100 0000
base clock BASE_APB3_CLK
OUTCLK_11_CTRL R/W
0x074
Output stage 11 control register for 0x0100 0000
base clock BASE_LCD_CLK
-
-
0x078 Reserved
-
OUTCLK_13_CTRL R/W
0x07C
Output stage 13 control register for 0x0100 0000
base clock BASE_SDIO_CLK
OUTCLK_14_CTRL R/W
0x080
Output stage 14 control register for 0x0100 0000
base clock BASE_SSP0_CLK
OUTCLK_15_CTRL R/W
0x084
Output stage 15 control register for 0x0100 0000
base clock BASE_SSP1_CLK
OUTCLK_16_CTRL R/W
0x088
Output stage 16 control register for 0x0100 0000
base clock BASE_UART0_CLK
OUTCLK_17_CTRL R/W
0x08C
Output stage 17 control register for 0x0100 0000
base clock BASE_UART1_CLK
OUTCLK_18_CTRL R/W
0x090
Output stage 18 control register for 0x0100 0000
base clock BASE_UART2_CLK
OUTCLK_19_CTRL R/W
0x094
Output stage 19 control register for 0x0100 0000
base clock BASE_UART3_CLK
OUTCLK_20_CTRL R/W
0x098
Output stage 20 control register for 0x0100 0000
base clock BASE_OUT_CLK
OUTCLK_21_CTRL R/W
0x09C to Reserved output stages
-
to
0x0AC
OUTCLK_25_CTRL
42.4.6.1
Frequency monitor register
The CGU can report the relative frequency of any operating clock. The clock to be
measured must be selected by software, while the fixed-frequency IRC clock fref is used
as the reference frequency. A 14-bit counter then counts the number of cycles of the
measured clock that occur during a user-defined number of reference-clock cycles. When
the MEAS bit is set, the measured-clock counter is reset to 0 and counts up, while the
9-bit reference-clock counter is loaded with the value in RCNT and then counts down
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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