UM10430 Datasheet, PDF (246/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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• Level-sensitive interrupt pins can be HIGH- or LOW-active.
15.3.2 GPIO group interrupt features
• The inputs from any number of GPIO pins can be enabled to contribute to a combined
group interrupt.
• The polarity of each input enabled for the group interrupt can be configured HIGH or
LOW.
• Enabled interrupts can be logically combined through an OR or AND operation.
• Two group interrupts are supported to reflect two distinct interrupt patterns.
• The GPIO group interrupts can wake up the part from sleep, deep-sleep or
power-down modes.
15.3.3 GPIO port features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
15.4 Introduction
The GPIO pins can be used in several ways to set pins as inputs or outputs and use the
inputs as combinations of level and edge sensitive interrupts.
15.4.1 GPIO pin interrupts
From all available GPIO pins, up to eight pins can be selected in the system control block
to serve as external interrupt pins (see <tbd>). The external interrupt pins are connected
to eight individual interrupts in the NVIC and are created based on rising or falling edges
or on the input level on the pin.
15.4.2 GPIO group interrupt
For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks
(GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are
enabled to generate interrupts and what the active polarities of each of those inputs are.
The GPIO grouped interrupt registers also select whether the interrupt output will be level
or edge triggered and whether it will be based on the OR or the AND of all of the enabled
inputs.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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