UM10430 Datasheet, PDF (738/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

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Remark: In this mode the u_clk period is allowed to be 4x the serial clock period.
32.6.2.2
Synchronous master mode
Synchronous master mode is enabled by setting the CSRC register bit to ‘1’. In this mode,
the external clock is generated internally by the baud-rate generation logic and is used to
clock the input and output serial data. The functionality of the baud-rate generation is
described in Section 32.5.12.1. Auto-baud is not supported during synchronous mode.
The 1x baud rate clock is used to shift out the serial output data and to sample the serial
input data.
Synchronous master mode behaves similar to the slave mode, except that the serial input
data is not registered at the interface but is clocked in the UART clock domain at the
sampling edge of the serial clock.
During synchronous master mode, when start and stop bits are transmitted, the user can
enable the external clock continuously using cscen bit of the Synchronous Mode Control
register. This allows the connected slave to transmit data even when no data is
transmitted by the master itself.
32.6.3 RS-485/EIA-485 modes of operation
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the UART to set the parity error and generate an interrupt.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored
and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it
will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The
processor can then read the address byte and decide whether or not to enable the
receiver to accept the following data.
While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be accepted
and stored in the RXFIFO regardless of whether they are data or address. When an
address character is received a parity error interrupt will be generated and the processor
can decide whether or not to disable the receiver.
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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