UM10430 Datasheet, PDF (778/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP
Semiconductors
Table
Bit
0
72_RS5yX:m_D(SbMSSoSAPlP_ED1)M) _{bAitCdoenstcrorilpRtDfdRio}eo_ieesrgn_ascti_hebcseilrtveeip_erdr_et.D(_cioDeMnMivAeA_EC_FnIR_FaOb- _la_eisd_. d_Wenr_he_aes_bns_let0_dhx_,i^D_s4_o^CR0_tb^A_h^h0_it^F_e8^aT_irsw^p3^D_s0^t_i^R_s^e_e2^A_e^D_t^r4^FR_tr^T3_oe(^AS^4D_c^F_oS_e^:TR_ni^AP^LD_ve^FR_e0^P₁^TAD)_D^C,_,^DFR_D0_M^T1RAx_MA8FDA4^TFRx_A0_Ti^ADx_s0_DFRC^STRDA_Rv0ARFDS5a^TF_e^AR0^P_lTs^FAD_u2^0T_eDFR4e^/T_{tRDA1ARDFTFDARTRFADTADFRTFRDATADRF}
1
TXDMAE
Transmit DMA Enable. When this bit is set to one 1, DMA 0
for the transmit FIFO is enabled, otherwise transmit DMA
is disabled
31:2 -
Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.
34.7 Functional description
34.7.1 Texas Instruments synchronous serial frame format
Figure 100 shows the 4-wire Texas Instruments synchronous serial frame format
supported by the SSP module.
CLK
FS
DX/DR
a. Single frame transfer
MSB
LSB
4 to 16 bits
CLK
FS
DX/DR
MSB
LSB
MSB
LSB
4 to 16 bits
4 to 16 bits
b. Continuous/back-to-back frames transfer
Fig 100. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
Frames Transfer
For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the
transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be
transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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