UM10430 Datasheet, PDF (980/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

NXP Semiconductors
Table 926. CGU0 base clocks …continued
Number Name
Frequency
[1]
13
BASE_SDIO_CLK
150 MHz
14
BASE_SSP0_CLK
150 MHz
15
BASE_SSP1_CLK
150 MHz
16
BASE_UART0_CLK
150 MHz
17
BASE_UART1_CLK
150 MHz
18
BASE_UART2_CLK
150 MHz
19
BASE_UART3_CLK
150 MHz
20
BASE_OUT_CLK
150 MHz
UM10430 ^DRAFT
Description
Base clock for
Base clock for
Base clock for
Base clock for
D_{SSSURDSSAADCPPRIFROT01hT}^AaD_0c^F_a^TRp_{rADtdeFRTrrADeDFR4aTRA2dAFDe:TFRrATADpDFRTRDApARFDeTFARnTFADdTDFRiTRDAxARDFTFDARTRFADTADFRTFRDATADRF}
Base clock for UART1
Base clock for UART2
Base clock for UART3
Base clock for CLKOUT pin
[1] Maximum frequency that guarantees stable operation of the LPC18xx.
Table 927 shows all available input clock sources for each clock generator.
Table 927. Clock sources for clock generators with selectable inputs
Clock generators
Clock sources
PLL0 PLL1
(USB0)
IDIVA
/4
IDIVB
/16
IDIVC
/16
32 kHz oscillator yes
yes
yes
yes
yes
IRC 12 MHz
yes
yes
yes
yes
yes
ENET_RX_CLK yes
yes
yes
yes
yes
ENET_TX_CLK yes
yes
yes
yes
yes
GP_CLKIN
yes
yes
yes
yes
yes
Crystal oscillator yes
yes
yes
yes
yes
PLL0 (USB0)
no
yes
yes
no
no
PLL1
yes
no
yes
yes
yes
IDIVA
yes
yes
no
yes
yes
IDIVB
yes
yes
no
no
no
IDIVC
yes
yes
no
no
no
IDIVD
yes
yes
no
no
no
IDIVE
yes
yes
no
no
no
IDIVD
/16
yes
yes
yes
yes
yes
yes
no
yes
yes
no
no
no
no
IDIVE
/256
yes
yes
yes
yes
yes
yes
no
yes
yes
no
no
no
no
Table 928. Clock sources for output stages
Output stages (d = default clock source)
Clock sources
32 kHz oscillator no no -
IRC 12 MHz
d no -
ENET_RX_CLK no no -
yes yes yes -
ddd-
yes yes yes -
yes yes yes yes yes -
ddddd-
yes yes yes yes yes -
yes yes yes yes yes yes yes yes
dddddddd
yes yes yes yes yes yes yes yes
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User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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