UM10430 Datasheet, PDF (473/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller

UM10430 NXP Semiconductors
Chapter 21:
Table 395. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000
Bit Symbol Description
15:4 -
19:16 FETB
Reserved
Flush endpoint transmit buffer for physical IN endpoints.
Writing a one to a bit(s) will clear any primed buffers.
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FETB0 = endpoint 0
...
FETB3 = endpoint 3
31:20 -
Reserved
-
-
21.6.20 USB Endpoint Status register (ENDPTSTAT)
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set
by hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the
ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon
the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer
ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH
register.
Remark: These bits will be momentarily cleared by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.
Table 396. USB Endpoint Status register (ENDPTSTAT - address 0x4000 71B8) bit description
Bit Symbol Description
Reset
value
3:0 ERBR
Endpoint receive buffer ready for physical OUT endpoints.
0
This bit is set to 1 by hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register.
ERBR0 = endpoint 0
...
ERBR3 = endpoint 3
15:4 -
Reserved
-
19:16 ETBR
Endpoint transmit buffer ready for physical IN endpoints 3 to 0.
0
This bit is set to 1 by hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register.
ETBR0 = endpoint 0
...
ETBR3 = endpoint 3
31:20 -
Reserved
-
Access
RO
-
RO
-
21.6.21 USB Endpoint Complete register (ENDPTCOMPLETE)
Each bit in this register indicates that a received/transmit event occurred and software
should read the corresponding endpoint queue to determine the transfer status. If the
corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set
simultaneously with the USBINT.
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Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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