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UM10430 Datasheet, PDF (23/1164 Pages) NXP Semiconductors – LPC18xx ARM Cortex-M3 microcontroller
UM10430 NXP Semiconductors
Table 7. Boot mode when OTP BOOT_SRC bits are programmed
Boot mode
Boot pins
BOOT_SRC BOOT_SRC BOOT_SRC
bit 3
bit 2
bit 1
0
0
0
BOOT_SRC
bit 0
0
UART
0
0
0
1
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SPIFI
0
0
1
0
Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
EMC 8-bit 0
0
1
1
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit 0
1
0
0
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit 0
1
0
1
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0
0
1
1
0
Boot from USB0.
USB1
0
1
1
1
Boot from USB1.
SPI (SSP) 1
0
0
0
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8[1].
USART3 1
0
0
1
Boot from device connected to USART3 using pins
P2_3 and P2_4.
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Table 8. Boot mode when OPT BOOT_SRC bits are zero
Boot mode
USART0
P2_9
LOW
P2_8
LOW
P1_2
LOW
P1_1
LOW
Description
Boot from device connected to USART0 using pins P2_0 and
P2_1.
SPIFI
LOW
LOW
LOW
HIGH Boot from Quad SPI flash connected to the SPIFI interface on
P3_3 to P3_8[1].
EMC 8-bit
LOW
LOW
HIGH
LOW Boot from external static memory (such as NOR flash) using CS0
and an 8-bit data bus.
EMC 16-bit
LOW
LOW
HIGH
HIGH Boot from external static memory (such as NOR flash) using CS0
and a 16-bit data bus.
EMC 32-bit
LOW
HIGH LOW
LOW Boot from external static memory (such as NOR flash) using CS0
and a 32-bit data bus.
USB0
LOW HIGH LOW HIGH Boot from USB0.
USB1
LOW HIGH HIGH LOW Boot from USB1.
SPI (SSP)
LOW
HIGH HIGH
HIGH Boot from SPI flash connected to the SSP0 interface on P3_3,
P3_6, P3_7 and P3_8[1].
USART3
HIGH LOW
LOW
LOW Boot from device connected to USART3 using pins P2_3 and
P2_4.
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
<Document ID>
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
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